This application is based on Japanese Patent Application 2001-067165, filed on Mar. 9, 2001, the entire contents of which are incorporated herein by reference.
a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor integrated circuit device having a moisture-proof ring formed in a peripheral area of a chip and its manufacture method.
b) Description of the Related Art
A semiconductor integrated circuit device is formed by fabricating a number of elements in a semiconductor chip and forming a multi-layer wiring structure on the semiconductor chip. The multi-layer wiring structure is made of a plurality of wiring layers and a plurality of interlevel insulating films for insulating wiring layers. In order to have electrical connection between different wiring layers, via holes are formed through an interlevel insulating film before an upper level wiring layer is formed on this interlevel insulating film. When the upper level wiring layer is formed, this layer also fills the via holes.
A resist mask is formed on the wiring layer formed on the interlevel insulating film, and by using the resist mask as an etching mask, the wiring layer is etched to form a wiring pattern. Deposits and the like on the side walls of a wiring pattern are removed by chemicals such as alkali. Thereafter, in order to provide electrical insulation between the wiring patterns of the same level wiring layer and between upper and lower wiring patterns, an interlevel insulating film of silicon oxide or the like is formed by plasma CVD.
As the material of a wiring layer, aluminum (Al), tungsten (W) and the like capable of being etched have been used conventionally. In order to prevent the surface of a wiring pattern from being oxidized during an ashing process of removing the resist mask after the wiring pattern is formed, an anti-oxidation layer of TiN or the like is formed on the main wiring layer of Al or W.
An interlevel insulating film of silicon oxide or the like has the nature of transmitting moisture in the ambient air therethrough. If moisture in the air reaches a semiconductor element, the semiconductor element characteristics are deteriorated. In order to prevent invasion of moisture in the ambient air, a passivation film of SiN or the like having a moisture-proof ability is formed on the uppermost insulating layer and in addition an electrically conductive moisture-proof ring is formed in the chip peripheral area.
The moisture-proof ring is formed by forming a ring trench surrounding a circuit area in a loop shape through etching at the same time when via holes are formed through an interlevel insulating film, and then filling a wiring layer in the ring trench and patterning the wiring layer in a wiring pattern forming process.
An integration degree of semiconductor integrated circuit devices is continually required to be raised. In order to raise the integration degree, semiconductor elements are made finer or smaller to form a more number of semiconductor elements in a unit area. As semiconductor elements are made finer, the density of wiring patterns formed above the semiconductor elements increases more. As the wiring density increases, the width of each wiring pattern becomes narrower and the distance between adjacent wiring patterns becomes shorter.
Assuming the same thickness of a wiring layer, as the wiring pattern width is made narrower, the wiring resistance increases. As the distance between adjacent wiring patterns is made shorter, the capacitance between wiring patterns increases. In order to suppress an increase in the wiring resistance, it is required to thicken the wiring layer. In order to maintain the cross section of a wiring pattern constant, a reduction in the wiring pattern width is required to be compensated by an increase in the wiring pattern thickness.
However, as a wiring layer is made thick, the opposing area between adjacent wiring patterns increases so that the capacitance between the wiring patterns increases further. Increases in the wiring resistance and capacitance between wiring patterns lower the signal transmission speed. Since higher integration and lower power consumption are main issues of memory devices, wiring material such as Al has been used as conventional.
A main issue of logic circuits is an arithmetic operation speed so that a reduction in a signal transmission speed is required to be suppressed as much as possible. It is therefore desired to lower a wiring resistance and a parasitic wiring capacitance. In order to lower a wiring resistance, it has been proposed to use refractory metal such as Cu as the wiring material having a resistivity lower than that of Al. In order to lower a parasitic wiring capacitance, it has been proposed to lower a dielectric constant of an insulating film which provides electric insulation between wiring patterns. For example, as an insulating film having a low dielectric constant, a fluorine-containing silicon oxide film (FSG: fluorine-containing silicate glass) or the like is used.
A Cu wiring layer is difficult to be patterned through etching. From this reason, a damascene process is used to form a Cu wiring pattern. In the damascene process, a trench is formed in an insulating film, a Cu layer is formed filling the trench, and an unnecessary Cu layer on the insulating film is removed by chemical mechanical polishing (CMP) or the like. It is known that the damascene process includes a single damascene process and a dual damascene process.
In the single damascene process, a photoresist pattern for forming via holes is formed on the underlying insulating film and via holes are formed through etching. After the photoresist pattern is removed, a Cu layer is deposited and an unnecessary Cu layer is removed by CMP. Another insulating layer is formed and a photoresist pattern for forming wiring patterns is formed on the insulating layer. Wiring pattern trenches are formed in the overlying insulating layer. After the photoresist pattern is removed, a Cu layer is deposited and an unnecessary Cu layer is removed by CMP.
In the dual damascene process, a via hole forming photoresist pattern is formed on an insulating layer to form via holes through etching. A wiring pattern forming photoresist pattern is formed on the same insulating layer to form wiring pattern trenches in the insulating layer. Thereafter, a Cu layer is deposited, completely filling the via holes and wiring pattern grooves by the same process, and an unnecessary Cu layer is removed by CMP.
If an underlying Cu wiring layer is exposed, while the photoresist pattern is removed by ashing after via holes are formed, the exposed surface of the Cu wiring layer is oxidized. In order to prevent oxidation of the Cu wiring layer surface, an anti-oxidation film having an etching stopper function is formed covering the surface of the Cu wiring pattern. This anti-oxidation film serving also as an etching stopper is made of, for example, SiN.
If the etching stopper/anti-oxidation film is formed under an insulating film, a via hole passing through the insulating film and exposing the etching stopper/anti-oxidation film is formed through etching. At this stage, the photoresist pattern is removed by ashing. Thereafter, the etching stopper/anti-oxidation film exposed at the bottom of the via hole is removed. In the following, the etching stopper/ant-oxidation film is simply called an etching stopper film (layer).
Cu has the nature of diffusing into an insulating film of silicon oxide or the like and degrading the dielectric characteristics and insulating characteristics of the insulating layer. In order to prevent diffusion of Cu, a barrier layer of TiN, TaN or the like is formed prior to forming a Cu wiring layer, and then the Cu wiring layer is formed on the barrier layer.
In forming a moisture-proof ring when Cu wiring is adopted, the insulating film in the chip peripheral area is etched in a loop trench shape at the same time when the insulating film is etched for forming via holes and wiring pattern trenches, and thereafter a barrier layer and a Cu wiring layer are formed in the moisture-proof ring trench at the same time when the barrier layer and Cu wiring layer are formed in the circuit area.
In the etching of fine patterns, it is known that the micro-loading effect occurs which shows that an etching rate in a narrow area is slower than that in a broad area. A via hole diameter is determined by circuit design to be, for example, a minimum size (rule). If the width of a moisture-proof ring trench is set larger than the via hole diameter, the moisture-proof ring trench is over-etched due to the micro-loading effect. From this reason, the width of the moisture-proof ring trench is designed to be equal to the via hole diameter.
With reference to FIGS. 9A to 9C, description will be made on how a via hole and a moisture-proof ring are etched. Where appropriate, each constituent element in a circuit area is represented by a reference numeral affixed with a character c, and each constituent element in a moisture-proof area is represented by a reference numeral affixed with a character r.
As shown in FIG. 9A, underlying wiring patterns include an underlying wiring pattern 121c in a circuit area and a conductive ring 121r in a moisture-proof ring area. An etching stopper layer 122 of SiN or the like is formed covering these underlying wiring patterns, and an interlevel insulating film 123 is formed on the etching stopper layer 122.
On the interlevel insulating film 123, a resist pattern PR is formed having via hole openings VO and a moisture-proof ring trench opening RO. The diameter of the via hole opening VO and the width of the moisture-proof ring trench opening RO are equal. By using such a photoresist pattern PR as an etching mask, the interlevel insulating film 123 is etched.
Although the diameter of the via hole opening VO and the width of the moisture-proof ring trench opening RO are equal as shown in FIG. 9A, etching progresses faster for a moisture proof ring trench RT than for a via hole VH as shown in FIG. 9B. Therefore, there is a height difference d between the bottom of the via hole VH and the bottom of the moisture-proof ring trench RT.
As shown in FIG. 9C, etching the interlevel insulating film 123 terminates faster at the moisture-proof ring trench RT. As the etching continues thereafter, the via hole VH is completely etched. During this etching, the moisture-proof ring RT continues to be over-etched.
During the period after the moisture ring trench RT is completely etched and before the etching of the via hole VH is completed, the etching stopper film 122 exposed at the bottom of the moisture-proof trench RT is being over-etched. For example, an etch rate ratio of a silicon nitride film to a silicon oxide film has a relatively small value of 1/10 to 1/15. However, in order to reliably leave the etching stopper film 122, it is necessary to form the etching stopper film 122 thick.
SiN of the etching stopper film has a high dielectric constant. If the etching stopper film 122 is made thick, a parasitic capacitance between wiring patterns under the etching stopper film 122 increases. In order to make the etching stopper film 122 thinnest and reliably leave it under the moisture-proof ring trench, it is desired to set the etch rate of the via hole and that of the moisture-proof ring trench substantially equal.
It is an object of the present invention to provide a novel structure of a semiconductor integrated circuit device having a moisture-proof ring, and a manufacture method for such a device.
It is another object of the present invention to provide a structure of a semiconductor integrated circuit device capable of minimizing an etch rate difference between a via hole and a moisture-proof ring trench during a damascene process, and a manufacture method for such a device.
It is a further object of the present invention to provide a method of manufacturing a semiconductor device capable of suppressing a reduction in the thickness of an etching stopper film during etching via holes and a moisture-proof ring trench, and minimizing damages to underlying wiring patterns.
According to one aspect of the present invention, there is provided a semiconductor integrated circuit device, comprising: a semiconductor substrate having a circuit area defined in a central portion of the semiconductor substrate and a moisture-proof ring area surrounding the circuit area in a loop-shape; a plurality of semiconductor elements formed in the circuit area; a plurality of insulating layers formed on the semiconductor substrate; cavities for forming wiring layers of a multi-layer structure, the cavities being formed in each of the insulating layers in the circuit area, each of the cavities in each wiring layer of the multi-layer structure having a lower via hole and an upper wiring pattern trench; wiring layers of the multi-layer structure formed in the cavities including a lower via conductor filled in the via hole and an upper wiring pattern filled in the wiring pattern trench, the via conductor forming an electrical connection between the wiring patterns of different wiring layers or between the wiring pattern and the semiconductor element; moisture-proof ring trenches of a multi-layer structure corresponding to the cavities for forming the wiring layers of the multi-layer structure, the moisture-proof ring trenches surrounding the circuit area of the semiconductor substrate in a loop-shape and formed through the insulating layers in the moisture-proof ring area, a width of each of the moisture-proof ring trenches corresponding to a corresponding one or ones of the via holes being set smaller than a minimum diameter of the via holes; and a conductive moisture-proof ring filled in corresponding one of the moisture-proof ring trenches and made of a same layer as the via conductor and the wiring pattern.
By narrowing the width of the moisture-proof ring trench, the etch rate of the moisture-proof ring trench lowers. It is possible to reduce the etch rate difference between the via holes and moisture-proof ring trench.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming a plurality of semiconductor elements in a circuit area of a semiconductor substrate having the circuit area defined in a central portion of the semiconductor substrate and a moisture-proof ring area surrounding the circuit area in a loop-shape; (b) forming an etching stopper layer and an insulating layer in this order on the semiconductor substrate, the etching stopper layer and the insulating layer covering the plurality of semiconductor elements; (c) forming a resist pattern on the insulating layer, the resist pattern having a plurality of via hole forming openings having a smallest diameter of a first value in an area corresponding to the circuit area and a loop-shape ring trench forming opening having a width of a second value smaller than the first value in an area corresponding to the moisture-proof ring area; (d) etching the insulating film by using the resist pattern as a mask to form via holes and a ring trench exposing the etching stopper layer; (e) removing the resist pattern; (f) removing the exposed etching stopper layer to complete the via holes and the ring trench; (g) forming a conductive layer on the insulating layer, the conductive layer filling insides of the via holes and the ring trench; and (h) removing an unnecessary portion of the conductive layer.
Although the moisture-proof ring trench has a high aspect ratio along its width direction, it has a considerably low aspect ratio in its longitudinal direction. In contrast, the via hole has a high aspect ratio along an omnidirection in the in-plane of the via hole.
The etch rate of a via hole is slower than the etch rate of a moisture-proof ring trench having the same size because of the micro-loading effect. By setting the width of the moisture-proof ring trench smaller than the diameter of the via hole, an etch rate difference can be reduced. By reducing the etch rate difference, an over-etch amount of an etching stopper film at the bottom of the moisture-proof ring trench can be reduced and an etching margin can be made broad and damages to the underlying wiring layer can be reduced.
A semiconductor integrated circuit device having a moisture-proof ring and a desired performance can be formed without oxidizing the surface of a wiring material layer constituting the moisture-proof ring.